Semiconductor memory device

ABSTRACT

A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of a capacitor via the memory cell transistor. Thereafter, when a plate line connected to a plate side of the capacitor is driven from voltage VPL to voltage VPH and the voltage of the storage node is increased due to coupling, the voltage VDL of the bit line is reduced to the voltage VDP, and the voltage excessively written into the storage node is reduced in accordance with a level of a threshold voltage of the memory cell transistor, thereby reducing a variation in the voltage of the storage node due to a variation in the threshold voltage.

CROSS-REFERENCE TO RELATED APPLICATION

This is a continuation application of U.S. Ser. No. 11/280,170, filedNov. 17, 2005 (now allowed).

The present application claims priority from Japanese PatentApplications No. JP 2004-335886 filed on Nov. 19, 2004 and JP2005-172077 filed on Jun. 13, 2005, the contents of which are herebyincorporated by reference into this application.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a semiconductor memory device such as adynamic random access memory (DRAM). More particularly, the inventionrelates to a technology effectively applied to the semiconductor memorydevice, in which a plate electrode is driven so as to increase theamount of writing charge to a memory cell.

BACKGROUND OF THE INVENTION

According to the examination by the inventors of the present invention,the following micro-fabrication technology for DRAM is known.

In order to microfabricate and highly integrate the memory cells ofDRAM, capacitors that realize a large capacity in a limited base area ofthe memory cells and miniaturized transistors are required. A seriousproblem at the time of microfabricating memory cell transistors is thethickness reduction of gate oxide. When a gate length of MOS transistorsis shortened, it is necessary to reduce the thickness of the gate oxidein order to suppress a short channel effect.

In DRAM, however, since an N channel MOS transistor is used for a memorycell, a maximum writing voltage for an “H” side of a storage node isVPP−VT which is obtained when the voltage VPP on an “H” side of a wordline to be applied to a gate of the memory cell transistor reduces by athreshold voltage VT, and the threshold voltage VT is not allowed to bereduced in order to maintain data retention characteristics. For thisreason, the voltage of the word line cannot be readily reduced.Therefore, in comparison with the MOS transistors to be used for logicproducts, the thickness of the gate oxide of memory cell transistors islarge, and thus the micro-fabrication thereof is difficult.

In order to solve such a problem, for example, Japanese PatentApplication Laid-Open Publication No. 11-260054 (Patent Document 1)discloses DRAM in which a plate electrode of a memory cell is driven toincrease the writing voltage to the memory cell. In this method, thevoltage on the “H” side of a word line is reduced. By doing so, theproblem that the writing of the “H” side data becomes insufficient iscompensated by driving a plate electrode. As a result, since thethickness of a gate oxide of a memory cell transistor can be reduced,the memory cell can be microfabricated.

SUMMARY OF THE INVENTION

Incidentally, as a result of the examination for the micro-fabricationof DRAM by the inventors of the present invention, the followings becomeapparent.

For example, the technology in the Patent Document 1 has the followingproblem. In the miniaturized transistor to be used for the memory cell,the threshold voltage VT varies widely, and a range of the variationbecomes nearly 1 V in DRAM with large capacity. When a plate is drivenin the case where the threshold voltage of the memory cells varieswidely, the voltage to be written into the memory cells varies widely.More specifically, when amplitude of a plate is increased in order towrite a voltage sufficiently into a cell with a large threshold voltage,an excessively high voltage is written into a cell with a low thresholdvoltage, and as a result, reliability of the memory transistor isdegraded.

This problem will be described with reference to FIG. 20 and FIG. 21.FIG. 20 is a circuit diagram illustrating a configuration example of apart of a DRAM memory array in which a plate is driven in asemiconductor memory device examined as a premise of the presentinvention. FIG. 21 is an operation waveform diagram illustrating oneexample of the operation in the semiconductor memory device of FIG. 20.

The DRAM memory array shown in FIG. 20 includes a word line WL0 drivenby a main word line MWLB or a sub-word driver selection line FX, bitlines BLT and BLB, a memory cell which is disposed at an intersectionbetween the word line WL0 and the bit line BLT, a sense amplifier SAdisposed between the bit lines BLT and BLB, and the like. The memorycell includes a memory cell transistor and a capacitor Cs, and one endof the capacitor Cs (on the side of the memory cell transistor) is astorage node SN and the other end thereof is a plate line PL.

The sense amplifier SA includes a transfer gate TGC driven by senseamplifier isolation signals SHR0 and SHR1, a reading/writing port IOPwhich connects the bit lines BLT and BLB to a local IO line pair (LIOline pair) by a column selection line YS, a precharge circuit PCC whichprecharges the bit lines BLT and BLB by means of the activation of aprecharge signal BLEQ, and a cross-coupled amplifier CC which amplifiesa voltage difference between the bit lines BLT and BLB by driving acommon source line of PMOS CSP and a common source line of NMOS CSN.Note that, although a part of the configuration is shown here, theactual DRAM memory array includes a lot of memory cells, senseamplifiers SA and the like.

For example, an operation as shown in FIG. 21 is performed in thisconfiguration. When a bank activation command ACT is inputted from anoutside of a chip, one signal SHR1 of the sense amplifier isolationsignals SHR and the precharge signal BLEQ are deactivated in the senseamplifier SA specified by an address. When the main word line MWLB isreduced to VKK in a row decoder and the sub-word driver selection lineFX is activated in an array control circuit, the selected word line WL0is activated from VKK to VPP. VKK is a power supply voltage on alow-level side of the word line generated by a negative power supplyvoltage generating circuit, and VPP is a power supply voltage on ahigh-level side.

In the memory cell selected by the word line WL0, the memory celltransistor becomes conductive, and a signal is read onto the bit lineBLT. FIG. 21 illustrates an example in which a ground voltage VSS iswritten into the memory cell and “L” signal is generated. Thereafter, inthe sense amplifier SA, the common source line of PMOS CSP is driven toVDL and the common source line of NMOS CSN is driven to the groundvoltage VSS, and the signals on the bit lines BLT and BLB are amplified.In this state, the memory chip can receive a read command RD or a writecommand WRT. FIG. 21 illustrates the case where the write command WRT isinputted.

In this manner, the column selection line YS with the selected addressis activated, and the write data is written from the LIO line pair. Awaveform at the time of inverse writing in which the bit line BLT isdriven to “H” is shown here.

Thereafter, the voltage of the plate line PL of the selected memory cellfalls from VPH to VPL. Since the memory cell transistor is an N channelMOS transistor, the maximum voltage which can be written to the storagenode SN becomes VPP−VT when the threshold voltage is VT. In this DRAMmemory array, the “H” level VPP of the word line is reduced to about thepower supply voltage VDD (for example, 1.8 V). Further, since a lot ofminiaturized transistors are used as the memory cell transistors, thevariation in the threshold voltage VT is very large and is nearly 1V.For example, when a design center value is set to 0.7 V, the minimumvalue of the threshold voltage VT becomes 0.2 V and the maximum valuethereof becomes 1.2 V.

Then, when the bit line voltage VDL is set to, for example, 1.3 V, sinceVPP−VT=1.6 V in the memory cell with low threshold voltage (LVT-cell),the memory cell transistor is ON, and VDL of 1.3 V is written into thestorage node SN. In the memory cell with intermediate threshold voltage(MVT-cell) and a memory cell with high threshold voltage (HVT-cell),however, the memory cell transistors are cut off during theamplification, only voltages of up to 1.1 V and 0.6 V are written intothe respective storage nodes SN. More specifically, the voltage in thestorage nodes SN at the time of writing varies in a range of 0.6 V to1.3 V in accordance with the threshold voltage VT of the memory celltransistors.

In this state, after the precharge command PRC is inputted, when thevoltage of the plate line PL of the selected memory cell is returnedfrom VPL to VPH, the voltage of the storage node SN increases by ΔPL(=VPH−VPL) due to the coupling from the capacitor Cs. Since the memorycell transistor is cut off or a conductance is very small in the memorycell into which “H” is written, the increased voltage ΔPL is retained.However, since the memory cell transistor is in a sufficiently ON statein the memory cell into which “L” is written, the voltage is returned tothe ground voltage VSS immediately. Therefore, the amount of theaccumulated charge can be increased by ΔPL.

When ΔPL is set to, for example, 0.7 V so that the writing voltage ofthe memory cell with the highest threshold voltage (HVT-cell) isincreased to VDL, voltages of 1.3 V or higher are written into all thememory cells. Therefore, the reading signal amount and a margin forretention time in a next cycle can be increased. However, since voltageVDL of up to 1.3 V can be originally written into the cell with lowthreshold voltage (LVT-cell), it is increased up to 2.0 V when thevoltage further increases by ΔPL. If the word line is deactivated inthis state, a high voltage is still applied to the memory celltransistor at the time of standby. For this reason, the reliability ofthe device is degraded, and the micro-fabrication of the memory celltransistor becomes difficult.

In order to solve the above problems, an object of the present inventionis to provide a semiconductor memory device, which is usefulparticularly for micro-fabrication of DRAM.

The above and other objects and novel characteristics of the presentinvention will be apparent from the description of this specificationand the accompanying drawings.

The typical ones of the inventions disclosed in this application will bebriefly described as follows.

A semiconductor memory device according to the present inventioncomprises: a plurality of memory cells each having a MOS transistor anda capacitor, in which a gate of the MOS transistor is a selectionterminal, one of source and drain of the MOS transistor is an I/Oterminal, and the other of the source and drain is connected to astorage node of the capacitor; a plurality of word lines respectivelyconnected to the selection terminals of the plurality of memory cells;complementary bit lines respectively connected to the I/O terminals ofthe plurality of memory cells; sense amplifiers which are connected toone ends of the complementary bit lines and amplify a voltage differencebetween the complementary bit lines to latch the amplified voltage; andmeans which, after one of the plurality of word lines is activated andat the time when the sense amplifier is activated, one of thecomplementary bit lines is amplified to a first voltage, and the othercomplementary bit line is amplified to a second voltage lower than thefirst voltage, reduces the voltage of the complementary bit lineamplified to the first voltage to a third voltage lower than the firstvoltage at a first time and then deactivates the one of word lines.

More specifically, in a DRAM memory cell, the amount of writing(including rewriting) charges varies in some cases due to a variation ina threshold voltage of an MOS transistor (memory cell transistor), andthis variation in the amount of the writing charges is reduced bydischarging excessive writing charges in a final phase of the writingbefore the word lines are deactivated. As a result, problems ofreliability such as durability of elements, breakdown voltage andleakage which are caused by excessive writing charges can be solved, andthus the micro-fabrication of the semiconductor memory device can berealized.

Herein, the sense amplifier can be a so-called cross-coupled amplifier,and in this case, the above-mentioned means can be realized by reducingthe first voltage of the common source node of PMOS in the cross-coupledamplifier to the fourth voltage lower than the first voltage. Further,the first time can be later than the time at which a precharge commandis inputted into the semiconductor memory device. That is, the excessivewriting charges into the storage node are discharged in a short timejust before the word lines are deactivated, so as to adjust the writingcharges.

The above-mentioned means can be used in combination with a so-calledoverdrive of the sense amplifier. In this case, after the word lines areactivated, the common source line of PMOS is driven to a fifth voltagehigher than the first voltage, and then is driven to the first voltageand further to the fourth voltage.

Also, a semiconductor memory device according to the present inventioncomprises: a plurality of memory cells each having a MOS transistor anda capacitor, in which a gate of the MOS transistor is a selectionterminal, one of source and drain of the MOS transistor is an I/Oterminal, and the other of the source and drain is connected to astorage node of the capacitor; a plurality of word lines respectivelyconnected to the selection terminals of the plurality of memory cells;complementary bit lines respectively connected to the I/O terminals ofthe plurality of memory cells; a plurality of plate lines respectivelyconnected to terminals on an opposite side of the storage nodes of thecapacitors in the plurality of memory cells; sense amplifiers which areconnected to one ends of the complementary bit lines and amplify avoltage difference between the complementary bit lines to latch theamplified voltage; means which, after one of the plurality of word linesis activated and at the time when the sense amplifier is activated, oneof the complementary bit lines is amplified to a first voltage, and theother complementary bit line is amplified to a second voltage lower thanthe first voltage, drives a plate line corresponding to the one of wordlines from a sixth voltage to a seventh voltage higher than the sixthvoltage at a second time; and means which reduces the voltage of the bitline amplified to the first voltage to a third voltage lower than thefirst voltage at a first time and then deactivates the one of wordlines.

That is, particularly in the case of the DRAM memory cell adopting theplate driven scheme in which the plate lines are driven, the excessivewriting charges as mentioned above are frequently generated. Suchexcessive writing charges become the factors to deteriorate thereliability of the device in the micro-fabrication. However, such aproblem can be solved by providing the means as described above.

A semiconductor memory device according to the present inventioncomprises: a plurality of memory cells each having a MOS transistor anda capacitor, in which a gate of the MOS transistor is a selectionterminal, one of source and drain of the MOS transistor is an I/Oterminal, and the other of the source and drain is connected to astorage node of the capacitor; a plurality of word lines respectivelyconnected to the selection terminals of the plurality of memory cells;complementary bit lines respectively connected to the I/O terminals ofthe plurality of memory cells; sense amplifiers which are connected toone ends of the complementary bit lines and amplify a voltage differencebetween the complementary bit lines to latch the amplified voltage; acommon source line of PMOS and a common source line of NMOS connected tothe sense amplifier; and first, second and third drivers which drive thecommon source line of PMOS, wherein the sense amplifier is across-coupled amplifier, and the first driver is connected to a firstpower supply voltage, the second driver is connected to a fourth powersupply voltage, and the third driver is connected to a fifth powersupply voltage.

Herein, the fourth power supply voltage can be lower than a half of thefirst power supply voltage. More specifically, the first power supplyvoltage is a writing voltage VDL on the “H” side of the complementarybit lines, and the fourth power supply voltage is used when theexcessive writing charges are discharged. In an actual case, it ispreferable that, by setting the voltage to a value lower than VDL/2, thevoltage on the “H” side of the bit line is reduced at high speed so asto discharge the excessive writing charges present in the storage nodeat high speed. Note that, in an actual case, since the voltage of thebit line is not decreased to lower than the threshold voltage due to aninfluence of the threshold voltage of a P channel MOS transistor of thecross-coupled amplifier, the fourth power supply voltage can be groundvoltage VSS (0V) without any problems. Further, the fifth power supplyvoltage is, for example, a voltage for the overdrive of the senseamplifier.

The effect obtained by typical aspects of the present invention is thatit is possible to realize the micro-fabrication of a semiconductormemory device.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1A is a plan view illustrating one configuration example of anentire chip in a semiconductor memory device according to one embodimentof the present invention;

FIG. 1B is a plan view illustrating one configuration example of amemory block in FIG. 1A in a semiconductor memory device according toone embodiment of the present invention;

FIG. 2 is a circuit diagram illustrating one configuration example ofmemory arrays and sense amplifier rows in the semiconductor memorydevice in FIG. 1A and FIG. 1B;

FIG. 3 is a plan view illustrating one example of a detailed arrangementrelationship among the sense amplifier rows, sub-word driver rows andplate driver rows in the semiconductor memory device in FIG. 1A and FIG.1B;

FIG. 4 is a circuit diagram illustrating one example of a detailedconfiguration of the sense amplifier rows in the semiconductor memorydevice in FIG. 2;

FIG. 5 is a circuit diagram illustrating one example of a configurationof a cross area in the semiconductor memory device in FIG. 1A and FIG.1B;

FIG. 6 is an operation waveform diagram illustrating one example of theoperation in the semiconductor memory device in FIG. 1A and FIG. 1B;

FIG. 7 is a circuit diagram illustrating a modified example of theconfiguration of the cross area in FIG. 5;

FIG. 8 is a schematic diagram illustrating one example of a scheme ofgenerating a voltage to be used in a CS line driver in the cross area ofFIG. 7;

FIG. 9 is a waveform diagram illustrating one example of an operation inthe case where the cross area of FIG. 7 is used in the semiconductormemory device in FIG. 1A and FIG. 1B;

FIG. 10A is a waveform chart of a main part in the operation of FIG. 6reproduced by circuit simulation;

FIG. 10B is a graph illustrating a relationship between a thresholdvoltage and a writing voltage in the operation;

FIG. 11 is an operation waveform diagram illustrating one modifiedexample of the operation in FIG. 6 in the semiconductor memory device inFIG. 1A and FIG. 1B;

FIG. 12 is an operation waveform diagram illustrating one modifiedexample of the operation in FIG. 6 in the semiconductor memory device inFIG. 1A and FIG. 1B;

FIG. 13A is a diagram illustrating one example of a layout of the memoryarray from an activate region to a storage node of a transistor in thesemiconductor memory device in FIG. 1A and FIG. 1B;

FIG. 13B is a diagram illustrating one example of a layout of the memoryarray from a plate electrode to a plate line in the semiconductor memorydevice;

FIG. 14 is a diagram illustrating one example of a sectionalconfiguration taken along the line A-A′ in the layout of FIG. 13A andFIG. 13B;

FIG. 15A is a diagram illustrating one example of a layout of a memoryarray from an active region to a storage node of a transistor differentfrom FIG. 13A in the semiconductor memory device in FIG. 1A and FIG. 1B;

FIG. 15B is a diagram illustrating one example of a layout from a plateelectrode to a plate line different from FIG. 13B in the semiconductormemory device;

FIG. 16A is a diagram illustrating one example of a layout of a memoryarray from an active region to a storage node of a transistor differentfrom FIG. 13A in the semiconductor memory device in FIG. 1A and FIG. 1B;

FIG. 16B is a diagram illustrating one example of a layout from a plateelectrode to a plate line different from FIG. 13B in the semiconductormemory device;

FIG. 17A is a diagram illustrating one example of a layout of a memoryarray from an active region to a storage node of a transistor differentfrom FIG. 16A in the semiconductor memory device in FIG. 1A and FIG. 1B;

FIG. 17B is a diagram illustrating one example of a layout from a plateelectrode to a plate line different from FIG. 16B in the semiconductormemory device;

FIG. 18 is a circuit diagram illustrating one example of a configurationof a sub-word driver row and a plate driver row in the semiconductormemory device in FIG. 1A and FIG. 1B;

FIG. 19 is a waveform diagram illustrating one example of an operationwaveform in the sub-word driver row and the plate driver word in FIG.18;

FIG. 20 is a circuit diagram illustrating a configuration example of apart of a DRAM memory array in which the plate is driven in asemiconductor memory device, which is examined as a premise of thepresent invention;

FIG. 21 is an operation waveform diagram illustrating one example of theoperation in the semiconductor memory device in FIG. 20;

FIG. 22 is a circuit diagram illustrating one example of a modifiedconfiguration of the memory arrays and the sense amplifier rows of FIG.2 in the semiconductor memory device in FIG. 1A and FIG. 1B; and

FIG. 23 is an operation waveform diagram illustrating one modifiedexample of the operation of FIG. 6 in the semiconductor memory device inFIG. 1A and FIG. 1B.

DESCRIPTIONS OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings. Note that componentshaving the same function are denoted by the same reference symbolsthroughout the drawings for describing the embodiment, and therepetitive description thereof will be omitted.

FIG. 1 1A and FIG. 1B are plan views showing examples of the chipconfiguration in the semiconductor memory device according to thepresent invention, in which FIG. 1 is a plan view illustrating oneconfiguration example of an entire chip and FIG. 1B is a plan viewillustrating one configuration example of memory blocks in FIG. 1A.

The semiconductor memory device shown in FIG. 1A and FIG. 1B is a DRAMadopting a plate driven scheme. An entire configuration of a memory chipCHIP is, as shown in FIG. 1A for example, roughly divided into a controlcircuit CNTL, I/O circuits DQC and memory blocks BLK. A clock, anaddress and a control signal are inputted into the control circuit CNTLfrom the outside of the memory chip CHIP, and an operation mode of thememory chip CHIP is determined and the predecode of an address isperformed. The I/O circuits DQC have an I/O buffer and the like, andwrite data is inputted from the outside of the memory chip CHIP and readdata are outputted to the outside of the memory chip CHIP.

In the memory block BLK, as shown in FIG. 1B for example, a plurality ofmemory arrays ARY are arranged, and sense amplifier rows SAA, sub-worddriver rows SWDA, plate driver rows PLDA and cross areas XP are arrangedaround the memory arrays ARY. Further, on an outer periphery of thememory block BLK, column decoders YDEC and a main amplifier row MAA arearranged in parallel with the sense amplifier rows SAA, and row decodersXDEC and array control circuits ACC are arranged in parallel with thesub-word driver rows SWDA.

FIG. 2 is a circuit diagram illustrating one example of a configurationof the memory arrays and the sense amplifier rows in the semiconductormemory device in FIG. 1A and FIG. 1B. As shown in FIG. 2, the memoryarray ARY is composed of a plurality of memory cells MC. The memorycells MC are DRAM memory cells, and each memory cell is composed of oneMOS transistor (memory cell transistor) and one capacitor Cs. One of asource and drain of the MOS transistor is connected to a bit line BLT ora bit line BLB, the other one thereof is connected to a storage node SN,and a gate thereof is connected to a word line WL.

One terminal of the capacitor Cs is connected to the storage node SN,and the other terminal is connected to a plate line PL arranged inparallel with the word line WL. The bit lines BLT and BLB serve as a bitline pair (complementary bit line) BLT/B.

It is preferable that, different from normal DRAM, the plate line PL isdivided for each one word line WL and the divided plate lines PL arearranged in parallel with the word lines WL so that only the plate linePL of the memory cell MC where the word line WL is activated is driven.By doing so, while disturbance on the other memory cells MC in anon-selected state due to the driving of the plate line PL is beingreduced, voltages of the storage nodes SN can be increased. Further, thememory array ARY includes dummy memory cells DMC which have the similarconfiguration to those of the memory cells MC. The dummy memory cellsDMC are connected to dummy word lines DWL and dummy plate lines DPL, andare used for generating reference signals at the time of reading.

FIG. 3 is a plan view illustrating one example of a detailed arrangementrelationship among the sense amplifier rows, sub-word driver rows andplate driver rows in the semiconductor memory device in FIG. 1A and FIG.1B. As shown in FIG. 3, the sense amplifiers SA in the sense amplifierrows SAA are arranged alternately above and below the memory arrays ARY,and are connected in common to the bit line pairs BLT/B in the memoryarray ARY.

Similarly, sub-word drivers SWD in the sub-word driver rows SWDA andplate drivers PLD in the plate driver rows PLDA are respectivelyarranged alternately on the right and left of the memory arrays ARY, andare connected in common to the word lines WL and the plate lines PL inthe right and left memory arrays ARY. With such arrangements, in thesub-word driver rows SWDA and the plate driver rows PLDA, pitchesbetween the sub-word drivers SWD and between the plate drivers PLD canbe widened two times as wide as pitches between the word lines WL andbetween the plate lines PL in the memory arrays ARY. Therefore, themicro-fabrication is facilitated.

FIG. 4 is a circuit diagram illustrating one example of a detailedconfiguration of the sense amplifier row in the semiconductor memorydevice in FIG. 2. As shown in FIG. 4, a plurality of sense amplifiers SAare arranged in the sense amplifier row SAA, and the respective senseamplifiers SA are connected in common to the bit line pairs BLT/B in thememory arrays ARY which are adjacent to the sense amplifiers SA on bothsides. Each of the sense amplifiers SA includes a transfer gate TGC, aprecharge circuit PCC, a cross-coupled amplifier CC and areading/writing port IOP.

The transfer gate TGC is a circuit that connects the sense amplifier SAand the memory array ARY when a sense amplifier isolation signal (SHRsignal) is activated. The precharge circuit PCC equalizes the pair ofthe bit lines BLT and BLB when a bit line precharge signal (BLEQ signal)is activated, and precharges them to a bit line precharge level VBLR.The bit line precharge level VBLR is normally set to a midpoint VDL/2 ofa voltage VDL with bit line amplitude (the same level as a power supplyvoltage VCC from the outside of the chip or a level obtained bydecreasing it).

After a minute reading signal is generated on the bit lines BLT and BLBfrom the memory cell MC and the dummy memory cell DMC, the cross-coupledamplifier CC drives a common source line of PMOS CSP to a voltage VDLand drives a common source line of NMOS CSN to a ground voltage VSS, andthen, it amplifies one of the bit lines BLT and BLB with higher voltageto the voltage VDL and the other of bit lines BLT and BLB with lowervoltage to the voltage VSS, so as to latch the amplified voltage. Thereading/writing port IOP is a circuit that connects local IO lines (LIOlines) LIOT/B and the bit line pair BLT/B when the column selection lineYS is activated. Note that, the LIO lines LIOT/B are retained at aprecharge level at the time of standby in order to prevent currentconsumption in the non-selected sense amplifier row SAA.

FIG. 5 is a circuit diagram illustrating one example of a configurationof the cross area in the semiconductor memory device in FIG. 1A and FIG.1B. The cross area XP includes an SHR signal driver SHD, an LIO lineprecharge circuit REQ, a read/write gate RGC, a CS line driver CSD, a CSline precharge circuit SEQ, a BLEQ signal driver EQD, an FX line driverFXD and a PX line driver PXD.

A complementary signal SHRB of an SHR signal is inputted into the SHRsignal driver SHD, and its inverted signal is outputted. When aread/write enable signal RWE is in a deactivated state, namely, in a VSSlevel, the LIO line precharge circuit REQ precharges the LIO linesLIOT/B to a voltage VPC. The read/write gate RGC is a circuit thatconnects the LIO lines LIOT/B and the main IO lines MIOT/B when theread/write enable signal RWE is in an activated state, namely, has avoltage VCL (used as a power supply voltage for a peripheral circuit atthe same level as the external VCC level or the level obtained bydecreasing it).

The CS line driver CSD is the circuit that drives the common source lineof NMOS CSN to the ground voltage VSS when the sense amplifier enablesignal of NMOS SAN is in an activated state, drives the common sourceline of PMOS CSP to the voltage VDL (“H” level of the bit line) when afirst sense amplifier enable signal of PMOS SAP1B is in an activatedstate (VSS level), and drives the common source line of PMOS CSP to thevoltage VSP when a second sense amplifier enable signal of PMOS SAP2 isin an activated state (VCL level).

In this case, a P channel MOS transistor is used as a circuit thatdrives the common source line of PMOS CSP to voltage VDL, and an Nchannel MOS transistor is used as a circuit that drives the commonsource line of NMOS CSN to voltage VSP. Since the circuit for driving tovoltage VSP mentioned later is for temporarily decreasing a bit linevoltage on an “H” side at the time of writing, the N channel MOStransistor is used for it. As a result, the bit line voltage can bedecreased at high speed. However, it is also possible to use a P channelMOS transistor to form it.

As described above, the present invention is characterized in that afunction by which the level of the common source line of PMOS CSP wherethe sense amplifier SA is activated can be set to two kinds of voltagesVDL and VSP is provided in the CS line driver CSD. At this time, whenthe CS line driver CSD is arranged in the cross area XP, there is anadvantage that the area of the sense amplifier SA does not increase.

The CS line precharge circuit SEQ is a circuit that precharges thecommon source lines of PMOS and NMOS CSP and CSN to VDL/2 when the BLEQsignal is activated. The BLEQ signal driver EQD inputs a complementarysignal BLEQB of the precharge signal BLEQ and outputs its invertedsignal. The FX line driver FXD inputs a signal FXB and outputs itscomplementary signal to a sub-word driver selection line FX (FX line).

The PX line driver PXD inputs a plate timing signal PXS with voltage VCLamplitude and outputs a voltage to the plate control line (PX line). ThePX line is the line for driving the plate line PL. When the plate timingsignal PXS is deactivated, the plate voltage VPH at the normal time isoutputted to the PX line. On the other hand, when the plate timingsignal PXS is activated, the plate voltage VPL is outputted to the PXline. Note that, by providing the PX line driver PXD in the cross areaXP, a delay of the PX line can be reduced.

An operation of the semiconductor memory device will be described below.FIG. 6 is an operation waveform diagram illustrating one example of theoperation in the semiconductor memory device in FIG. 1A and FIG. 1B.

As shown in FIG. 6, when a bank activation command ACT is inputted fromthe outside of the memory chip, one SHR signal and the BLEQ signal aredeactivated in the sense amplifier row SAA specified by an address.Also, a dummy word line DWL1 of the dummy cell DMC which is in VPP levelin the activated state is deactivated and returned to a VKK level. VKKis a power supply voltage on a low level side of the word line, which isgenerated from a negative power supply generating circuit. As describedabove, by setting the level of the word line at the deactivated time tobe lower than the ground voltage VSS, a threshold voltage of the memorycell transistor can be set to a lower value, and the level VPP on the“H” side of the word line can be reduced.

Thereafter, when the main word line MWLB decreases to voltage VKK in therow decoder XDEC and the FX line is activated in the array controlcircuit ACC, the selected word line WL0 is activated to the voltage VPP.The memory cell transistor becomes conductive in the memory cell MCselected by the word line WL0, and a signal is read onto the bit lineBLT. FIG. 6 illustrates the example where the ground voltage VSS iswritten into the memory cell MC in advance and an “L” signal isgenerated. Further, also the dummy word line DWL1 is activatedsimultaneously with the activation of the word line WL0, and a referencesignal is generated onto the bit line BLB from the dummy memory cell DMCin which the precharge voltage VBLR is written.

At this time, the voltage VPH falls to voltage VPL in the plate line PL0of the selected memory cell MC and the plate line DPL1 of thecorresponding dummy memory cell DMC. When the plate line PL0 is drivenin such a manner, the voltage level reduces in the storage node SN ofthe selected memory cell MC and the dummy storage node DSN of the dummymemory cell DMC due to the coupling via the capacitor Cs, and thus,respective accumulated charges are read onto the bit lines BLT and BLBat high speed. When the voltage VPH is set to a middle value between thevoltage VDL and the ground voltage VSS, a voltage to be applied to acapacitor dielectric film of the memory cell becomes low at the time ofstandby, and the reliability is improved.

Thereafter, the common source line of PMOS CSP is driven to voltage VDLand the common source line of NMOS CSN is driven to ground voltage VSSin the sense amplifier SA, and a voltage difference between the bitlines BLT and BLB is amplified. In this state, the memory chip canreceive a read command RD or a write command WRT. FIG. 6 illustrates thecase where the write command WRT is inputted. The column selection lineYS with selected address is activated, and write data is written fromthe LIO lines LIOT/B. In this case, waveforms at the time of inversewriting in which the bit line BLT is driven to “H” are shown.

Since the memory cell transistor is the N channel MOS transistor, whenthe threshold voltage is set to VT, the maximum voltage which can bewritten into the storage node SN becomes VPP−VT. In the memory chip ofthe present invention, in order to reduce the thickness of a gate oxideof the memory cell transistor, the “H” level voltage VPP of the wordline is reduced to be close to the power supply voltage VDD (forexample, 1.8 V). Also, since a miniaturized transistor is used as thememory cell transistor and the number thereof is large, the variation inthe threshold voltage VT is very large and is nearly 1V, and when adesign center value is, for example, 0.7 V, the minimum value is 0.2 Vand the maximum value is 1.2 V.

As a result, when the bit line voltage VDL is set to 1.3 V for example,since VPP−VT=1.6 V in the memory cell with low threshold voltage VT(LVT-cell), the memory cell transistor is ON, and thus VDL of 1.3 can bewritten into the storage node SN. On the other hand, the memory celltransistor is in a cut-off state during amplification in the memory cellwith the intermediate threshold voltage VT (MVT-cell) and the memorycell with the high threshold voltage VT (HVT-cell), and thus only thevoltages of up to 1.1 V and 0.6 V are written into the respectivestorage nodes NS. More specifically, the voltage of the storage node SNat the time of writing has the variation in the range of 0.6 V to 1.3 Vin accordance with the threshold voltage VT of the memory celltransistor.

In this state, when the precharge command PRC is inputted and thevoltage VPL is returned to the voltage VPH in the plate line PL0 of theselected memory cell MC and the dummy plate line DPL1 of the dummymemory cell DMC, the voltages of the storage nodes SN and DSN increaseby ΔPL (=VPH−VPL) due to the coupling from the capacitors Cs. At thistime, since the memory cell transistor is cut off or a conductance ishigh in the memory cell MC into which “H” is written, the increasedvoltage ΔPL is retained, but since the memory cell transistor is in asufficiently ON state in the memory cell MC into which “L” is written,the voltage is returned to the ground voltage VSS immediately.Therefore, the accumulated amount of charges of the storage node SN inthe memory cell MC can be increased by ΔPL.

When ΔPL is set to, for example, 0.7 V so that the writing voltage ofthe memory cell with the highest threshold voltage VT (HVT-cell)increases to VDL, 1.3 V or higher is written into all the memory cellsMC. Therefore, the reading signal amount and a margin for retention timein a next cycle can be increased. However, since VDL of 1.3 V isoriginally written into the memory cell with low threshold voltage VT(LVT-cell), when the voltage further increases by ΔPL, it is increasedto 2.0 V. When the word line is directly deactivated in this state, ahigh voltage is kept being applied to the memory cell transistor at thetime of standby, and thus, the reliability of the device is degraded.

In the present invention, therefore, only the memory cell MC with lowthreshold voltage VT is selectively discharged, and writing voltages forthe storage nodes SN at the time of deactivation of the word line aremade uniform according to the following method. By doing so, thereliability of the device is enhanced. More specifically, the voltage ofthe common source line of PMOS CSP is decreased to voltage VSP by the CSline driver CSD mentioned in FIG. 5, for example, at the timing afterthe plate line PL is driven next to the input of the precharge commandPRC. By doing so, the bit line voltage on the “H” side is decreased toVDP (for example, 0.7 V).

As a result, in the memory cell transistor in the memory cell MC withlow threshold voltage VT, since an effective gate voltage VGS−VT becomes0.9 V (=(1.8−0.7)−0.2) and thus the transistor is ON strongly, thecharges in the storage node SN are discharged quickly. On the otherhand, since VGS−VT becomes 0.4 V in the memory cell with intermediatethreshold voltage VT and the transistor is ON weakly, the discharge isgentle. Since VGS−VT obtains a negative value in the memory cell withhigh threshold voltage VT, the transistor is retained in a cut-offstate.

As shown in FIG. 6, therefore, the voltage which is increased too highby the discharge of the excessively written charges is reduced in thememory cell with low threshold voltage VT (LVT-cell), and the voltagesare approximately maintained in the memory cell with intermediatethreshold voltage (MVT-cell) and the memory cell with high thresholdvoltage (HVT-cell). For this reason, variation in the writing voltagebecomes smaller than that in the threshold voltage VT. After such adischarge operation is ended, the word line WLO is allowed to fall, andthe BLEQ signal and the SHR signal are again activated and the bit linepair BLT/B is precharged.

When the above-described configuration and operation according to thepresent invention are used, the amount of charges to be written into thememory cells are increased by driving the plate, and retentioncharacteristics and an operation speed are improved. Simultaneously,even when the variation in the threshold voltage is wide, the variationin the amount of the writing charges can be reduced by means of theadjusting method which discharges excessive writing charges. As aresult, since it is possible to prevent a high voltage from beingapplied to the memory cell transistor for a long time, the reliabilityof the device can be improved. Also, since the word line voltage can bereduced, the thickness of the gate oxide of the memory cell transistorcan be reduced, and the micro-fabrication is achieved. As a result, themanufacturing cost can be reduced owing to the increase in capacity ofthe DRAM chip and reduction in chip size.

Incidentally, the description above shows the example where the level ofthe common source line of PMOS CSP when the sense amplifier SA isactivated is set to two kinds of voltages VDL and VSP in the CS linedriver CSD. In addition, as shown in FIG. 7, it is also possible tocombine an overdrive sense scheme therewith. FIG. 7 is a circuit diagramillustrating one example where its configuration in the cross area inFIG. 5 is modified.

The cross area XP in FIG. 7 is shown as a circuit configuration examplewhere the plate driven scheme and the overdrive sense scheme are used incombination with each other, and the configuration of the CS line driverCSD is different when compared with the circuit shown in FIG. 5. Morespecifically, a PMOS transistor, which temporarily drives the commonsource line of PMOS CSP to overdrive voltage VOD when an initial senseamplifier enable signal of PMOS SAP0B is activated, is added to the CSline driver CSD shown in FIG. 7. The voltage VOD is higher than thefinal “H” level voltage VDL of the bit line, and is for increasing thespeed of an amplifying operation of the sense amplifier SA. Note that,even when types of drivers are increased in such a manner, since the CSline driver CSD is arranged in the cross area XP, the area of the senseamplifiers is not increased, and the micro-fabrication can beadvantageously achieved.

FIG. 8 is a schematic diagram illustrating one example of a generatingscheme of a voltage to be used in the CS driver in the cross area ofFIG. 7. Since the overdrive voltage VOD is higher than the final “H”level voltage VDL of the bit line, as shown in FIG. 8 for example, theexternal power supply voltage VDD to be supplied from the outside of thememory chip CHIP can be directly used. The “H” level voltage VDL of thebit line is generated by reducing the external power supply voltage VDDby a voltage limiter DC1. The voltage VSP is required to have a valuelower than the bit line voltage VDP at the time of the dischargementioned in FIG. 6 by the threshold voltage of the PMOS transistor inthe cross-coupled amplifier CC. For this reason, it is desired that thevoltage VSP is reduced to be lower than a half of the bit line voltageVDL/2 by using a voltage limiter DC2, or the ground voltage VSS isdirectly used as the voltage VSP.

When the plate driven scheme and the overdrive sense scheme are combinedas described above, the operation is as shown in FIG. 9. FIG. 9 is awaveform diagram illustrating one example of the operation when thecross area in FIG. 7 is used in the semiconductor memory device of FIG.1A and FIG. 1B. In the operation waveforms shown in FIG. 9, differentfrom the operation waveforms in FIG. 6, the common source line of PMOSCSP is temporarily driven by the overdrive voltage VOD at the initialamplification by means of the sense amplifier SA. After the bit linepair BLT/B is sufficiently amplified, the common source line of PMOS CSPis driven to the voltage VDL. When such driving is carried out, thespeed of the amplifying operation of the bit line is increased at thetime of the reading operation and the rewriting operation. Thesubsequent operation is similar to that in FIG. 6.

FIG. 10A and FIG. 10 B are diagrams showing the operation of FIG. 6reproduced by circuit simulation, in which FIG. 10A is a waveform chartof a main part in the operation, and FIG. 10B is a graph illustrating arelationship between a threshold voltage and a writing voltage in theoperation. In FIG. 10A, as described with reference to FIG. 6, the wordline WL is activated to 1.8 V and the voltage of the plate line PL isreduced by 0.7 V. In this state, a signal is generated on the bit linesBLT and BLB. At this time, when the signal amplification of the bitlines BLT and BLB is started and inverse writing is performed, thevariation in writing voltage for the storage node SN occurs inaccordance with the difference in the threshold voltage VT.

Thereafter, when the voltage of the plate line PL is increased, thevoltage of the storage node SN in the memory cell MC into which “H” iswritten is increased, but the voltage of the dummy storage node DSN inthe dummy memory cell DMC on the “L” side is once increased and thenreturned to the ground voltage VSS immediately. In the memory cell MCinto which “H” is written, the voltage of the bit line BLT is decreasedfor a period shown by DC, thereby discharging the excessively writtencharges. As a result, the final writing voltage variation is reduced.

In the graph shown in FIG. 10B, the horizontal axis represents thethreshold voltage VT of the memory cell transistor, and a vertical axisrepresents the voltage VP at the period just after the plate driving andthe voltage VS at the period just after the discharge operation isperformed for 7 ns and the word line is deactivated in the storage nodeSN. If the variation range of the threshold voltage VT is 0.2 to 1.2 V,as shown in FIG. 10B, the maximum voltage VP of the storage node SN atthe period just after the plate driving is nearly 2.0 V, and thevariation AVP becomes 0.80 V. More specifically, when the dischargeoperation is not performed, an excessive voltage of 0.80 V is applied tothe memory cell transistor.

On the other hand, when the discharge operation is performed, since thevoltage of the storage node SN is finally discharged to the voltage VS,the maximum value is 1.3 V when VT is about 0.7 V and the variation AVSbecomes 0.34 V. That is, the excessive voltage to be applied to thememory cell transistor is suppressed to 43%. As a result, thereliability of the memory cell transistor is improved, and themicro-fabrication is facilitated.

FIG. 11 and FIG. 12 are operation waveform diagrams illustratingmodified examples of the operation in FIG. 6 in the semiconductor memorydevice of FIG. 1A and FIG. 1B. The operation shown in FIG. 11 relates tothe operation in FIG. 6 and illustrates the case where the operation forincreasing the voltage VPL of the plate line PL to the voltage VPH andthe driving of the common source line of PMOS CSP to the voltage VSP areperformed simultaneously. In FIG. 6, just after the voltage of the plateline PL is increased, the voltage of the storage node SN increases and ahigh voltage is applied to the memory cell transistor even for a shorttime.

On the other hand, in the operation shown in FIG. 11, since the voltageof the storage node SN is increased by the driving of the plate line PLsimultaneously with the discharge of the excessive charges from thememory cell with low threshold voltage VT, a peak voltage is notgenerated on the storage node SN. Therefore, the application of the highvoltage to the memory cell transistor can be suppressed, and thereliability of the device can be further improved, and themicro-fabrication can be facilitated.

Further, in the operation shown in FIG. 12 relative to the operation ofFIG. 11, the timing that the voltage VPH of the plate line PL isdecreased to the voltage VPL is delayed to the time after the activationof the sense amplifier. In this case, since the plate line PL hasconstant voltage at the time of reading a signal onto the bit line pairBLT/B, the generation of the signal after the activation of the wordline is slightly delayed, but the bit line precharge voltage VBLR can bedirectly used as a reference voltage at the time of the amplification bythe sense amplifier. As a result, the dummy memory cell DMC becomesunnecessary, and the chip size can be reduced. In the operation shown inFIG. 12, in addition to the change in the timing of the plate line PL,the common source line of PMOS CSP is temporarily driven by theoverdrive voltage VOD at the time of the activation of the senseamplifier, and thus the operating speed of the sense amplifier isincreased.

FIG. 13A and FIG. 13B are diagrams showing examples of the layout of thememory array in the semiconductor memory device in FIG. 1, in which FIG.13A is a diagram illustrating an layout from an active region to astorage node of a transistor, and FIG. 13B is a diagram illustrating anlayout from a plate electrode to a plate line. FIG. 14 is a diagramillustrating one example of a sectional configuration taken along theline A-A′ in the layouts of FIG. 13A and FIG. 13B. The layouts shown inFIG. 13A and FIG. 13B include a plurality of word lines WL0 to WL4 and aplurality of adjacent bit line pairs BLT/B, and the complementaryoperation is performed by the bit line pairs BLT/B. Note that, in thelayout, the bit line pair BLT/B intersects one word line, and the layoutis called as a folded bit-line memory array.

In the layout shown in FIG. 13A, a plurality of active regions ACT areformed in parallel with the bit lines, and the two word lines extend oneach active region ACT. In each active region ACT, two memory celltransistors using the two word lines as respective gates are formed. Oneends of sources/drains of the two memory cell transistors are connectedto the bit lines via common bit line contacts BC, respectively, and theother ends are connected to respectively different storage nodes SN viadifferent storage node contacts SC. A horizontal width of each storagenode SN in the bit line direction can be a size which overlaps the twoadjacent word lines.

In the layout shown in FIG. 13B, a plurality of plate electrodes PLE areformed so as to correspond to each of the storage nodes SN of FIG. 13A,and a plurality of plate lines PL0 to PL4 are formed so as to correspondto each of the plurality of word lines WL0 to WL4. More specifically,the layout of the plural plate lines PL0 to PL4 and the plural plateelectrodes PLE can be approximately the same as the layout of the pluralword lines WL0 to WLA and the plural storage nodes SN in FIG. 13A. Inthis case, since a horizontal width of each plate electrode PLE in thebit line direction may be a size which overlaps the two adjacent platelines, each plate electrode PLE can be connected to any one of the twooverlapped plate lines via a plate contact PC.

Each DRAM memory cell has, as shown in FIG. 14, an N channel MOStransistor (memory cell transistor) formed on a semiconductor substratePW and a stack capacitor provided on the bit line BL. In FIG. 14, thetwo word lines WL are arranged on the active region ACT in thesemiconductor substrate PW isolated by a dielectric film SiO₂, the twoword lines WL are used as the gates of the memory cell transistor, and Ntype diffusion layer regions N to be the sources/drains of the memorycell transistor are provided on the semiconductor substrate PW.

A contact CB is arranged on the N type diffusion layer region N betweenthe two word lines WL, and a bit line contact BC is arranged on thecontact CB. The bit line BL which is formed in a direction perpendicularto the extending direction of the word lines WL is arranged on the bitline contact BC. On the other hand, the contact CB is arranged on each Ntype diffusion layer region N on the outside of the two word lines WL,and the storage node contact SC is arranged on each contact CB. Thestorage node SN with a concave shape (cylinder shape) which is formed onan inner wall of a hole in an interlayer dielectric film (not shown) isarranged on each storage node contact SC, and the plate electrode PLE isembedded in each storage node SN, and they form the capacitor Cs withinterposing a capacitor dielectric film CI therebetween.

The plate contact PC is arranged on each plate electrode PLE, and it isconnected to the plate line PL arranged in the word line direction. FIG.14 illustrates the stack capacitor in which only insides of the storagenode SN electrodes formed in deep holes are used as the capacitor. Sincethe use of this capacitor can isolate the plate electrodes PLE on thestorage nodes SN, an isolation process is advantageously facilitated.Alternatively, the capacitor using not only the insides of the storagenode SN electrodes but also the outsides thereof is also available. Inthis case, however, the capacity can be increased, but since the plateelectrodes PLE have to be isolated below the storage node SN electrodes,the isolation process becomes complicated.

In FIG. 13B, the contact is provided on every other storage node SN, andthe memory cells selected by the word lines WL0 to WL4 are connected tothe corresponding plate lines PL0 to PL4, respectively. Further, thestorage nodes SN and the plate electrodes PLE have a horizontally longshape in the folded bit line layout, and they extend over the region ofthe two word lines WL.

Accordingly, since the plate lines PL are arranged in an approximatelylinear shape and the contacts are arranged alternately on the adjacentplate lines PL, the plate lines PL can be easily isolated for each wordline. Further, since the active regions ACT of the MOS transistor areformed in a linear pattern, the manufacturing process is facilitated. Asa result, the micro-fabrication can be easily realized, and since thebit line and the reference bit line from which a signal is generated arepresent in the same array, a noise can be advantageously reduced.

FIG. 15A and FIG. 15B are diagrams showing examples of the layout of thememory array different from that in FIG. 13A and FIG. 13B in thesemiconductor memory device in FIG. 1, in which FIG. 13A is a diagramillustrating a layout of a memory array from the activate region to thestorage node of a transistor, and FIG. 15B is a diagram illustrating alayout from the plate electrode to the plate line. The layouts shown inFIG. 15A and FIG. 15B are called as a quasi folded bit-line memory array(quarter pitch memory array), and include the plural word lines WL0 toWL4 and the plural bit lines, in which the complementary operation isperformed by the bit line pair BL/BLB which sandwiches one bit line.

In the layouts shown in FIG. 15A and FIG. 15B, the active regions ACTdescribed in FIG. 13 are formed obliquely with respect to the bit lines,and the two storage node contacts SC in each active region ACT areformed so as to sandwich the bit line. When this layout is used, theshape of the storage node SN can be approximately circular, and thus thecapacity of the capacitor can be easily secured even when themicro-fabrication is advanced. Also, since the bit line and thereference bit line for generating a signal are present in the samememory array even in the quasi folded bit-line memory array, the noisecan be advantageously reduced.

FIG. 16A and FIG. 16B are diagrams showing examples of the layout of thememory array different from that of FIG. 13A and FIG. 13B in thesemiconductor memory device in FIG. 1, in which FIG. 16A is a diagramillustrating a layout from the active region to the storage node of atransistor, and FIG. 16B is a diagram illustrating a layout from theplate electrode to the plate line. The layouts shown in FIG. 16A andFIG. 16B are called as an open bit-line memory array where only one ofthe bit line pair BLT/B intersects one word line. In addition, thelayouts are a narrow bit-line pitch type open bit-line memory arraywhere the pitches of the bit lines BL are narrowed.

In this memory array, the DRAM memory cells are provided to allintersections between the bit lines BL and the word lines WL. The pairedbit lines BLT and BLB are present in the memory arrays on the oppositesides via the sense amplifiers. In FIG. 16A and FIG. 16B, the pluralactive regions ACT are formed continuously in the direction of the bitlines BL, and the plural word lines WL extend on each active region ACT.However, one of the three word lines WL is used as an element isolatinggate ISO, and it is driven to “L” level or is connected to a fixedvoltage of “L” level according to need.

When the word lines WL are arranged at the pitch of 2F (F: minimumprocessing dimension), the pitch of the bit lines BL can be set to 2F orless. Since the effective pitch of the word lines WL becomes 3F due tothe presence of the element isolating gate ISO, the size of the memorycell becomes 6F². Therefore, the size of the memory cell can be reducedto be smaller than 8F², which is the size of the memory cell in thefolded bit-line memory array, and thus, this is useful for themicro-fabrication. Further, when this memory array is used, since thestorage nodes SN in the memory cell selected by one word line WL arearranged linearly, the plate line PL can have a linear pattern. Further,since the pitch of the plate lines PL can be widened to 3F, themanufacturing process can be advantageously facilitated.

FIG. 17A and FIG. 17B are diagrams showing the examples of the layout ofthe memory array different from that in FIG. 16A and FIG. 16B in thesemiconductor memory device in FIG. 1A and FIG. 1B, in which FIG. 17A isa diagram illustrating a layout from the activate region to the storagenode of the transistor, and FIG. 17B is a diagram illustrating a layoutfrom the plate electrode to the plate line. The layouts shown in FIG.17A and FIG. 17B are the layout of a wide bit-line pitch type openbit-line memory array.

In this memory array, the DRAM memory cells are provided to all theintersections between the bit lines BL and the word lines WL. The pairedbit lines BLT and BLB are present in the memory arrays on the oppositesides via the sense amplifier. In FIG. 16A and FIG. 16B, the pluralactive regions ACT are formed obliquely with respect to the bit linesBL, and the two word lines WL extend on each active region ACT.

When the word lines WL are arranged at the pitch of 2F, the pitch of thebit lines BL becomes, for example, 3F. When this memory array is used,an array noise is higher than that of the folded bit-line memory array,but the size of the memory cell is 6F². More specifically, it can bereduced to be smaller than 8F² of the folded bit-line memory array.Further, since the pitch of the bit lines BL is wider than the pitch ofthe word lines WL, a coupling noise between bit lines can be reducedalso by the micro-fabrication, and the layout of the sense amplifierscan be advantageously facilitated.

FIG. 18 is a circuit diagram illustrating one example of a configurationof the sub-word driver row and the plate driver row in the semiconductormemory device in FIG. 1A and FIG. 1B. The sub-word driver row SWDA iscomposed of a plurality of sub-word drivers SWD, and the plate driverrow PLDA is composed of a plurality of plate drivers PLD. Further, asshown in FIG. 1B or the like, the plate driver row PLDA and the sub-worddriver row SWDA are arranged adjacent to each other around the memoryarray ARY.

The sub-word drivers SWD and the plate drivers PLD drive the word linesWL and the plate lines PL in the memory arrays ARY which are arranged onboth sides of the drivers SWD and PLD, respectively. At this time, oneword line WL is driven so as to correspond to one plate line PL. Asshown in FIG. 3, since the plate driver row PLDA and the sub-word driverrow SWDA are arranged alternately with respect to the memory array ARY,every other word lines WL (sub-word lines) and every other plate linesPL in the memory array ARY are connected to the sub-word drivers SWD andthe plate drivers PLD on the left and right, respectively.

The sub-word driver SWD is composed of two N channel MOS transistors andone P channel MOS transistor. In one N channel MOS transistor, the mainword line MWLB is connected to the gate, the word line WL is connectedto the drain, and the voltage VKK is connected to the source. In anotherN channel MOS transistor, the complementary word driver selection lineFXB is connected to the gate, the word line WL is connected to thedrain, and the voltage VKK is connected to the source.

In the P channel MOS transistor, the main word line MWLB is connected tothe gate, the word line WL is connected to the drain, and the sub-worddriver selection line FX is connected to the drain. As shown in FIG. 18,four sub-word driver selection lines FX0 to FX4 are arranged on onesub-word driver row SWDA, and one of the four sub-word drivers SWDselected by one main word line MWLB is selected, thereby activating oneword line WL.

The plate driver PLD is composed of one N channel MOS transistor and oneP channel MOS transistor. In the N channel MOS transistor, the word lineWL is connected to the gate, the plate line PL is connected to thedrain, and the plate control line PX is connected to the source. In theP channel MOS transistor, the word line WL is connected to the gate, theplate line PL is connected to the drain, and the power supply line ofthe plate voltage VPH is connected to the source.

FIG. 19 is a waveform diagram illustrating one example of the operationwaveform in the sub-word driver row and the plate driver row of FIG. 18.When the voltage of the main word line MWLB is decreased to voltage VKKin the row decoder XDEC and the FX line is activated in the arraycontrol circuit ACC, the selected word line WL0 is activated to voltageVPP.

When the word line WL0 is in a deactivated state, namely, in a voltageVKK level, the plate line PL is fixed to the voltage VPH. When the wordline WL0 is activated to the voltage VPP, the plate line PL and theplate control line PX (PX line) are connected. When a plate timingsignal PXS is “H”, the PX line driver in the cross area XP of FIG. 5outputs the voltage VPH to the PX line, and when the plate timing signalPXS is “L”, it outputs the voltage VPL to the PX line. By decreasing andincreasing the voltage of the PX line in this manner, the voltage of theplate line PL is also decreased and increased similarly.

FIG. 22 illustrates the memory array and the sense amplifier rows on itsboth sides in the case where the present invention is applied to a twincell array. The memory array is composed of a plurality of memory cellsMC. A twin DRAM cell is composed of two MOS transistors and twocapacitors, and two DRAM cells compose the memory cell. One of thesource and drain of the first MOS transistor is connected to the bitline BLT, the other thereof is connected to the storage node SN, and thegate thereof is connected to the word line WL. One terminal of the firstcapacitor is connected to the storage node SN, and the other terminal ofthe capacitor is connected to the plate line PL which is arranged inparallel with the word line. One of the source and drain of the secondMOS transistor is connected to the complementary bit line BLB, the otherthereof is connected to the storage node SNB, and the gate thereof isconnected to the word line WL. One terminal of the second capacitor isconnected to the storage node SNB, and the other terminal of thecapacitor is connected to the plate line PL which is arranged inparallel with the word line.

Different from a normal DRAM, when the plate line is divided for eachone word line and the divided plate lines are arranged in parallel withthe word lines so that only the plate line of the memory cell where theword line is activated is driven, disturbance to the other memory cellsin a non-selected state is reduced, and simultaneously accumulatedvoltages can be increased. When the plate is driven in this array, thesame level of coupling voltage is applied to the bit line BLT and thecomplementary bit line BLB, and thus, a dummy cell does not have to beprovided unlike FIG. 2. Further, since a signal is generated in both ofthe bit lines and the complementary bit lines, the amount of a signal tobe inputted into the sense amplifier increases, and thus the high-speedoperation is achieved. Alternatively, even when the power supply voltageof the sense amplifier is reduced, the large signal amount can beobtained. Therefore, data retention time can be lengthened and the powerconsumption can be reduced.

FIG. 23 illustrates a driving method of the twin cell array shown inFIG. 22. This example shows the case where the plate driving scheme ofFIG. 6 is applied to the twin cell array. The difference from FIG. 6 isthat a dummy cell is not necessary and a complementary signal isgenerated in the bit lines BLT and the complementary bit lines BLB.

The operation waveform of FIG. 23 shows the operation of the DRAM arrayaccording to one embodiment of the present invention. When the bankactivation command ACT is inputted from the outside of the chip, one ofthe sense amplifier isolating signals SHR and the precharge signal BLEQare deactivated in the sense amplifier row SAA specified by an address.When the voltage of the main word line MWLB is reduced to VKK in the rowdecoder and FX is activated in the array control circuit ACC, theselected word line WL0 is activated to VPP. In the memory cell selectedby the word line WL0, the cell transistor becomes conductive, and asignal is read onto the bit lines BLT and the complementary bit linesBLB. FIG. 23 illustrates an example where the voltage VSS is writteninto the storage node SN and the voltage VDL is written into the storagenode SNB and a signal “0” is generated. Further, the plate line PL ofthe selected cell is allowed to fall from VPH to VPL. When the plateline is driven in this manner, since the levels of SN and SNB in theselected cells are reduced by the coupling via a cell capacity, chargesare read into the bit lines at high speed. In this case, when VPH is setto an approximately middle value between VDL and VSS, since the voltageto be applied to the capacitor dielectric film in the memory cells isreduced at the time of standby, the reliability can be improved.

When the common source line of PMOS CSP is driven to VDL and the commonsource line of NMOS CSN is driven to VSS in the sense amplifiers, thesignals on the bit lines are amplified. In this state, the chip canreceive the read command RD or the write command WRT. The drawing showsthe case where the write command is inputted. The column selection lineYS of the selected address is activated, and the write data is writtenfrom the LIO line pair. In this case, the waveform at the time ofinverse writing in which BLT is driven to “H” is shown.

Since the memory cell is the N channel MOS, when the threshold value isset to VT, the maximum voltage which can be written to SN is VPP−VT. Inorder to reduce the thickness of the gate oxide of the memory celltransistor in the DRAM according to one embodiment of the presentinvention, VPP which is the H level of the word lines is reduced toabout the power supply voltage VDD (for example, 1.8 V). Further, sincea lot of miniaturized transistors are used as the memory celltransistors, the variation in the threshold value is very large and isabout 1V, and when the design center value is set to, for example, 0.7V, the minimum value becomes 0.2 V and the maximum value becomes 1.2 V.When the bit line voltage VDL is set to 1.3 V, for example, sinceVPP−VT=1.6 V in the cell with small threshold value (LVT-cell), the celltransistors are ON and VDL of 1.3 V is written into the storage node SN.In the cell with intermediate threshold value (MVT-cell) and in the cellwith high threshold value (HVT-cell), however, the memory celltransistors are cut off during the amplification, and only voltages ofup to 1.1 V and 0.6 V are written into the respective storage nodes.More specifically, the SN voltage at the time of writing varies in arange of 0.6 V to 1.3 V in accordance with VT of the cell transistors.

When the precharge command PRC is inputted in this state and the platePL of the selected cell is returned from VPL to VPH, the potential of SNincreases by ΔPL (=VPH−VPL) due to the coupling from the capacitor.Since the cell transistors are cut off in the cell on the SN side intowhich “H” is written, the increase ΔPL in the potential is retained, butsince the cell transistors are ON in the cell on the SNB side into which“L” is written, the voltage is returned to VSS immediately. Therefore,the accumulated amount of charges can be increased by ΔPL. When ΔPL isset, for example, to 0.7 V so that the writing voltage of the memorycell with the highest threshold value (HVT-cell) is increased to VDL,1.3 V or higher is written into all the memory cells. For this reason,the reading signal amount and the margin for the retention time in thenext cycle can be increased. In the cell with low threshold value(LVT-cell), however, since VDL of 1.3 V is originally written, when thepotential further increases by ΔPL, the voltage is increased to 2.0 V.When the word lines are deactivated in this state, a high voltage isbeing applied to the memory cell transistors at the time of standby, andthe reliability of the device is degraded.

For its prevention, only the cells with low VT are selectivelydischarged and the SN writing voltages at the time of deactivating theword lines are made uniform according to the following method. By doingso, the reliability of the device is improved. More specifically, afterthe plate is driven, the voltage of the common source line of PMOS CSPis decreased to VSP so that the bit line voltage on the “H” side isdecreased to VDP (for example, 0.7 V). As a result, in the memory cellwith low threshold value (LVT-cell), the effective gate voltage VGS−VTbecomes 0.9 V (=(1.8−0.7)−0.2), and the transistor is ON strongly.Therefore, the charges of SN are discharged quickly. On the other hand,since VGS−VT becomes 0.4 V in the memory cell with intermediatethreshold voltage VT and the transistor is ON weakly, the discharge isgentle. Also, VGS−VT is negative and the cut-off state is maintained inthe cell with high threshold value. Therefore, as shown in the drawing,the potential which increases excessively is reduced in the cell withlow threshold value, and the potential in the cells with intermediateand high threshold values is maintained. As a result, the variation inthe writing voltage is reduced more than the variation in the thresholdvalue. After the discharging operation is ended, the word line is madeto fall and BLEQ and SHR are activated again, and the bit lines areprecharged.

As described above, by using the configurations and the operations shownin FIG. 22 and FIG. 23, it is possible to prevent a high voltage frombeing applied to the cell transistors for a long time. Therefore, thethickness of the gate oxide of the memory cell transistors can bereduced, and the micro-fabrication can be facilitated.

In the foregoing, the invention made by the inventors of the presentinvention has been concretely described based on the embodiments.However, it is needless to say that the present invention is not limitedto the foregoing embodiments and various modifications and alterationscan be made within the scope of the present invention.

The semiconductor memory device according to the present invention isparticularly effective when applied to DRAM products adopting the platedriven scheme, and it can be also applied to on-chip memories or thelike included in logic chips such microprocessors and DSP (DigitalSignal Processor).

1. (canceled)
 2. A semiconductor memory device comprising: a first memory array including a plurality of first memory cells; a second memory array including a plurality of second memory cells; a plurality of sense amplifiers located between the first memory array and the second memory array and amplifying a difference voltage between a signal from the first memory array and a signal from the second memory array; a plurality of first plate lines each coupled to ones of the plurality of first memory cells which are arranged in a row; and a plurality of second plate lines each coupled to ones of the plurality of second memory cells which are arranged in a row.
 3. A semiconductor memory device according to claim 2, wherein the first memory array further includes a plurality of first word lines parallel to the plurality of first plate lines, and wherein the second memory array further includes a plurality of second word lines parallel to the plurality of second plate lines.
 4. A semiconductor memory device according to claim 2, wherein each of the plurality of first and second memory cells has a transistor and a capacitor formed above the transistor.
 5. A semiconductor memory device according to claim 2, wherein each of the plurality of first and second memory cells has a transistor, a storage node contact coupled to the transistor, a storage node coupled to the storage node contact and having a concave shape which is formed on an inner wall of a hole in an insulator, an dielectric film formed on the storage node, and a plate electrode formed on the dielectric film.
 6. A semiconductor memory device according to claim 5, wherein each of the plurality of first and second memory cells further has a plate contact coupled to between the plate electrode and corresponding one of the plurality of first and second plate lines.
 7. A semiconductor memory device according to claim 5, wherein the plate electrode is only formed inside of the storage node.
 8. A semiconductor memory device according to claim 2, wherein the first memory array further has a plurality of first bit lines coupled to the plurality of sense amplifiers, and wherein the second memory array further has a plurality of second bit lines coupled to the plurality of sense amplifiers, wherein the plurality of sense amplifiers amplify the voltage difference between the plurality of first and second bit lines.
 9. A semiconductor memory device comprising: a plurality of memory cells each having a transistor; a storage node contact coupled to the transistor; a storage node coupled to the storage node contact, formed on an inner wall of a hole in an insulator, and having a concave shape; a dielectric film formed on the storage node; and a plate electrode formed on the dielectric film, wherein the plate electrodes of memory cells arranged in a row are coupled to each other.
 10. A semiconductor memory device according to claim 9, further comprising: a plate line coupled to the plate electrodes of memory cells arranged in a row, wherein each of the memory cells has a plate contact coupled between the plate line and the plate electrode.
 11. A semiconductor memory device according to claim 9, further comprising: a plurality of word lines coupled to the plurality of memory cells, wherein the plate line extend parallel to the plurality of word lines.
 12. A semiconductor memory device according to claim 9, wherein the capacitor is formed above the transistor.
 13. A semiconductor memory device according to claim 9, wherein the plate electrode is only formed inside of the storage node. 